1. Field of the Invention
This invention relates to the field of integrated circuit testing.
2. Description of the Related Art
An integrated circuit (IC) is a miniature electric circuit containing large numbers of discrete electronic circuit elements, such as transistors, resistors, capacitors, and diodes, which are packaged as a single unit with leads extending from it for input, output, and power-supply connections. The electronic circuit elements are formed by selective manipulation of a single chip of semiconductor material, often in combination with various other semi-conducting and/or conducting materials.
It is common in the art to roughly classify integrated circuits dependent upon their transistor density. Presently, there are effectively four common integrated circuit classifications: small-scale integrated circuits (SSIs); medium-scale integrated circuits (MSIs); large-scale integrated circuits (LSIs); and very-large-scale integrated circuit (VLSIs). Exactly what transistor densities constitute the various xe2x80x9cclassesxe2x80x9d varies, but at present SSIs typically include up to several tens of transistors, MSIs include from many tens to several hundred transistors; LSIs include from several hundred to a few thousand transistors; and VLSIs several hundred thousand or more. Most ICs in use today would constitute VLSIs.
One powerful feature of integrated circuits is the ability to use such integrated circuits to produce several levels of abstraction, which is useful for complete design. For example, integrated circuit design can be viewed at one level of abstraction in terms of discrete electronic circuit components (e.g., resistors, capacitors, inductors, transistors, diodes, etc.). Integrated circuit design can also be viewed at a next-higher layer of abstraction in terms of logic diagrams consisting of well-defined digital boolean logic circuits such as AND, NAND, OR, and NOR gates, where each such gate consists of well-defined congeries of the discrete electronic circuit elements. Integrated circuit design can also be viewed at yet a next-higher layer of abstraction known as Register Transfer Level (RTL), which consists of program-like statements describing the movement or processing of data between storage elements. Integrated circuits can also be viewed at a yet again higher layer of abstraction known as a functional block diagram layer, which shows the major subcomponents of a design. This is the level at which the highest conceptual design work is done.
Typically, IC design is done at the functional block diagram, RTL, and logic diagram levels. It is common for whole teams of people (and sometimes whole companies) to focus on various aspects of the design at various abstraction levels. However, as noted, the design process rarely proceeds at a lower level than that of logic diagrams. Below this level, it is common to program the desired logic diagram layouts into artificially intelligent software, which automatically produces discrete circuit component level diagrams to be enacted within the integrated circuit.
A particular type of IC is known as an Application Specific Integrated Circuit (ASIC). An ASIC is an integrated circuit that is designed and built to perform a particular set of functions via the use of an integrated circuit. One example of a way in which ASICs are commonly used is provide hardware implementations of computer software application programs. That is, use of ASICs allows system designers to work at and design at a software layer of abstraction in order to produce and debug a computer software application program to perform a desired function. Thereafter, the higher-level software layer of abstraction level of design can be translated to hardware level design via the use of various techniques well-known in the art, such as the Very High Speed Integrated Circuit Hardware Description Language (VHDL). The hardware level design can then be implemented in an IC, and since the IC will be designed to implement a particular application program, it has become common in the art to refer to such ICs as xe2x80x9cApplication Specificxe2x80x9d ICs, or ASICs.
Those skilled in the art will recognize that ASICs do not operate in a vacuum. That is, it is common, even in environments where ASICS are utilized, for the ASICs to interface and/or utilize one or more standard data processing system components, such as additional processing devices (e.g., one or more central processing units (CPUs), or dedicated graphics processors), communications channels (e.g., Peripheral Component Interface (PCI), or Advanced Graphics Processing (AGP) data buses).
In the past, the presence of ASICs in an environment typically meant that an independent, freestanding, IC existed for each ASIC present in addition to any other more standard integrated circuits necessary to support the system. However, efforts are now being made within the industry to move toward System-On-a-Chip (SOC) designs wherein any desired ASICs are actually designed into, and made part of, ICs which have one or more pre-existing xe2x80x9ccoresxe2x80x9d which provide the IC with logic sufficient to provide one or more standard functions, such as the functions of one or more standard data processing system components. It is common in the art to refer to non-core logic, such as an ASIC, as user-defined logic (UDL). An example of such a SOC is shown in FIG. 1.
With reference to FIG. 1, shown is a partial functional block diagram level related art integrated circuit SOC 100. As shown, contained within SOC 100 are CPU core 102, on-chip processor bus 104, on-chip bridge 106, system memory 107, on-chip peripheral component internal (PCI) bus 108, and peripheral bus components 110-114, and ASIC 116 (an example of UDL).
SOC 100 is a functional block diagram representation of various functional blocks performing their various functions. As referenced above, the actual implementation of the various functional blocks within any IC containing SOC 100 will be via the use of perhaps several hundred thousand interconnected discrete circuit level components.
As noted above, the discrete circuit level components are produced via the selective manipulation of a single piece of semiconductor material, where such selective manipulation usually includes the use of other semi-conducting and/or conducting materials. The discrete circuit level components are created via this selective manipulation.
The regions affected by the selective manipulation of the single piece of semiconductor material are almost unimaginably small. For example, current VLSI production procedures produce the discrete circuit components by manipulating material by use of sub-micron width (i.e., widths of less that (1/1,000,000) of a meter) lines drawn, or xe2x80x9cetched,xe2x80x9d in the semiconductor material. Furthermore, the sizes of the regions manipulated decrease virtually every week.
Due to the very small regions manipulated during VLSI production, errors invariably occur. This can be the result of contamination of the material, or minor variations in the length, width, or height of lines etched. These errors in production often result in errors in the behavior of the discrete electronic circuit level components.
As noted, the higher abstraction logic diagram level is designed using logic diagram level component circuits consisting of congeries of discrete circuit level components. Consequently, errors in production sufficient to produce errors in the behavior of the discrete circuit level components can xe2x80x9cpropagatexe2x80x9d upwards to the logic diagram level since the logic diagram circuits are built from congeries of these malfunctioning circuit components. If the errors are severe, then such malfunctioning will be very apparent in that the affected logic diagram level circuits will not function. However, if the malfunction is not severe, it is possible that the affected logic diagram level components will perform, but will perform in such a way that is out of design tolerances, which can cause a general system malfunction or failure as these logic diagram level errors xe2x80x9cpropagatexe2x80x9d up the abstraction-layer hierarchy to affect the RTL and functional block diagram level designs.
A principal way in which such a malfunction will manifest at the logic diagram level is that one or more of the logic diagram level circuits will perform their functions appropriately, but so slowly that they affect the design. Accordingly, testing has been devised in the art to ensure that the logic diagram level circuits are performing their functions within design tolerances. This testing basically amounts to the following: (1) defining at least one combinational logic path through a combinational logic circuit; (2) initializing the combinational logic circuit with a given set of inputs; (3) waiting until the combinational logic circuit becomes stable; (4) changing the logic levels of one or more of the set of inputs; and (5) and measuring the time it takes for output of the combinational logic circuit at the end of the defined path to change subsequent to the change in the set of inputs.
As noted, SOC 100 is composed of both vendor-defined xe2x80x9ccorexe2x80x9d logic and UDL. Also as noted, the finished IC is typically tested via the measurement of delays through various defined paths through the combinational logic of the IC. With respect to defined paths through the core logic, there are typically well-defined testing patterns and access points within the logic which are utilized to ensure that the core logic is functioning correctly. Likewise with respect to the standalone UDL; that is, there are typically well-defined testing patterns and access points within the logic which are utilized to ensure that the user-defined logic is functioning correctly. However, when the core logic and the user-defined logic are integrated onto one IC, such integration usually destroys the ability to independently test the UDL and the core logic. That is, subsequent to integration, newer overall path test patterns and logic paths are typically utilized.
There are several reasons why new test patterns and logic paths are utilized, but a primary reason is that within the art there is a lack of ability to practicably expose, separate, and/or test the UDL from the core logic subsequent to integration. It is not uncommon for designs to fail to satisfy the new testing criteria applied subsequent to integration of the UDL with the core logic.
When the integrated UDL and core logic fail to perform as expected, the reasons for such failure can range from the fact that the overall integration design was faulty or because either or both the UDL and core logic are not performing as they should (e.g., errors during production have caused either or both the UDL and core logic to malfunction). Those skilled in the art will recognize that it would be desirable to test the core logic and UDL independent of each other, in that well established testing criteria are available to test both the core and the UDL, and that it is desirable to localize the problem area or areas in the design if at all possible. However, at present there is in the art no practicable way to maintain the ability to independently access and test the core and UDL subsequent to integration. It is therefore apparent that a need exists in the art to allow the practicable independent access to and testing of the core and UDL subsequent to integration.
A method and circuit have been devised which allow the practicable independent access to and testing of UDL and core logic subsequent to integration of the UDL and core logic in an integrated circuit. The method and circuit allow direct access logic testing in integrated circuits. In one embodiment, an interface between integrated circuit core logic and integrated circuit user-defined logic is exposed, and the integrated circuit core logic and the integrated circuit user-defined logic is tested via the exposed interface. In another embodiment, an integrated circuit has logic selection circuitry connected with core logic and user-defined logic. The logic selection circuitry is used to selectively test the core logic and user-defined logic.
The foregoing is a summary and thus contains, by necessity, simplifications, generalizations and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and is not intended to be in any way limiting. Other aspects, inventive features, and advantages of the present invention, as defined solely by the claims, will become apparent in the non-limiting detailed description set forth below.